Invention Grant
- Patent Title: Method of locating failure site on semiconductor device under test
- Patent Title (中): 定位半导体器件故障现场的方法
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Application No.: US12229454Application Date: 2008-08-22
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Publication No.: US07928748B2Publication Date: 2011-04-19
- Inventor: Fayik Bundhoo , William Ng
- Applicant: Fayik Bundhoo , William Ng
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductgor
- Current Assignee: National Semiconductgor
- Current Assignee Address: US CA Santa Clara
- Agency: Vollrath & Associates
- Agent Jurgen K. Vollrath
- Main IPC: G01R31/302
- IPC: G01R31/302
Abstract:
In an analysis of a semiconductor device under test (DUT) using a Thermal Induced Voltage Alteration (TIVA) tool, the TIVA is connected to an output of the DUT and the DC component on the output is decoupled from the TIVA. The remaining AC component from the output is analyzed by the TIVA while scanning the DUT with a scanning laser to identify locations on the DUT that produce signal anomalies at the DUT output.
Public/Granted literature
- US20100045331A1 Method of locating failure site on semiconductor device under test Public/Granted day:2010-02-25
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