Invention Grant
- Patent Title: Interconnect structures for integration of multi-layered integrated circuit devices and methods for forming the same
- Patent Title (中): 用于集成多层集成电路器件的互连结构及其形成方法
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Application No.: US12174393Application Date: 2008-07-16
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Publication No.: US07928577B2Publication Date: 2011-04-19
- Inventor: Gurtej S. Sandhu , Nishant Sinha , John A. Smythe
- Applicant: Gurtej S. Sandhu , Nishant Sinha , John A. Smythe
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L23/52
- IPC: H01L23/52
Abstract:
Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.
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