A thin film transistor (“TFT”) substrate in which the size of a pixel TFT formed in a display area is reduced using a single slit mask, and the length of the channel area of a protection TFT constituting an electrostatic discharge protection circuit formed in a non-display area is formed larger than that of the pixel TFT using the same mask pattern. The TFT substrate includes a signal line and a discharge line formed on a substrate, a signal supply pad formed on one end of the signal line to supply a signal to the signal line, and an electrostatic discharge protection circuit including at least one protection TFT including a plurality of channels formed between the signal supply pad and the discharge line and/or between the signal line and the discharge line.