The present invention is a method that a redundant via is never added afterwards for a signal wiring or a clock wiring, but layout is performed using a multi-cut via from the beginning, which is used for laying out a semiconductor integrated circuit by a step (S32) of searching a wiring route that layout is possible using a multi-cut via regarding a net in a net list, a step (S33) of laying out a wiring corresponding to the net on the wiring route with using the multi-cut via, and a step (S70) of creating layout data of the semiconductor integrated circuit by repeating the steps S32 and S33.