Invention Grant
- Patent Title: Modeling asynchronous behavior from primary inputs and latches
- Patent Title (中): 从主要输入和锁存器建模异步行为
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Application No.: US12168888Application Date: 2008-07-07
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Publication No.: US07885801B2Publication Date: 2011-02-08
- Inventor: Zoltan T. Hidvegi , Yee Ja , Bradley S. Nelson
- Applicant: Zoltan T. Hidvegi , Yee Ja , Bradley S. Nelson
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Matthew B. Talpis; Jack V. Musgrove
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.
Public/Granted literature
- US20080295052A1 MODELING ASYNCHRONOUS BEHAVIOR FROM PRIMARY INPUTS AND LATCHES Public/Granted day:2008-11-27
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