Invention Grant
US07885799B2 Method for building MOS transistor model and method for verifying MOS transistor model
有权
MOS晶体管模型的构建方法及MOS晶体管模型的验证方法
- Patent Title: Method for building MOS transistor model and method for verifying MOS transistor model
- Patent Title (中): MOS晶体管模型的构建方法及MOS晶体管模型的验证方法
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Application No.: US11945991Application Date: 2007-11-27
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Publication No.: US07885799B2Publication Date: 2011-02-08
- Inventor: Juncheng Huang , Fangfang Zhao
- Applicant: Juncheng Huang , Fangfang Zhao
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Squire, Sanders & Dempsey L.L.P.
- Priority: CN200710042459 20070622
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
The present invention discloses a method for building an MOS transistor model enclosing statistical variation of noise, including: measuring noise in MOS transistors from different dies; creating a noise distribution diagram in accordance with the obtained noise data of the MOS transistors; adding a variation of noise parameter in at least one noise model file into a library file of MOS transistor to simulate noise in MOS transistors; if a simulation result does not cover the noise data in the noise distribution diagram, changing the variation of the noise parameter until the simulation result covers the noise data in the noise distribution diagram; if the simulation result covers the noise data in the noise distribution diagram, adding corresponding variation of the noise parameter into the library file of MOS transistor as the MOS transistor model enclosing statistical variation of noise. The model obtained by the present invention is more precise.
Public/Granted literature
- US20080319721A1 Method for Building MOS Transistor Model and Method for Verifying MOS Transistor Model Public/Granted day:2008-12-25
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