Invention Grant
- Patent Title: Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
- Patent Title (中): 用这种方法形成微电子工件和微电子工件中互连的方法
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Application No.: US11951751Application Date: 2007-12-06
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Publication No.: US07884015B2Publication Date: 2011-02-08
- Inventor: Marc Sulfridge
- Applicant: Marc Sulfridge
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment, for example, is directed to a method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies. The individual dies include integrated circuitry and a terminal electrically coupled to the integrated circuitry. The method can include forming a first opening in the substrate from a back side of the substrate toward a front side and in alignment with the terminal. The first opening has a generally annular cross-sectional profile and separates an island of substrate material from the substrate. The method can also include depositing an insulating material into at least a portion of the first opening, and then removing the island of substrate material to form a second opening aligned with at least a portion of the terminal. In several embodiments, the method may include constructing an electrically conductive interconnect in at least a portion of the second opening and in electrical contact with the terminal.
Public/Granted literature
Information query
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