Invention Grant
US07883936B2 Multi layer low cost cavity substrate fabrication for PoP packages
有权
PoP封装的多层低成本空腔衬底制造
- Patent Title: Multi layer low cost cavity substrate fabrication for PoP packages
- Patent Title (中): PoP封装的多层低成本空腔衬底制造
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Application No.: US12618859Application Date: 2009-11-16
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Publication No.: US07883936B2Publication Date: 2011-02-08
- Inventor: Prema Palaniappan , Masood Murtuza , Satyendra S Chauhan
- Applicant: Prema Palaniappan , Masood Murtuza , Satyendra S Chauhan
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Yingsheng Tung; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/50
- IPC: H01L21/50
Abstract:
In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).
Public/Granted literature
- US20100062567A1 Multi Layer Low Cost Cavity Substrate Fabrication for POP Packages Public/Granted day:2010-03-11
Information query
IPC分类:
