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US07883629B2 Technique for patterning differently stressed layers formed above transistors by enhanced etch control strategies 有权
通过增强的蚀刻控制策略对形成在晶体管上方的不同应力层进行图案化的技术

Technique for patterning differently stressed layers formed above transistors by enhanced etch control strategies
Abstract:
During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch rate and, thus, the performance of the respective etch process. In other cases, highly efficient etch indicator species may be incorporated into the stressed dielectric layers or may be formed on a surface portion thereof with reduced layer thickness, thereby providing an enhanced endpoint detection signal without creating the negative effects of silicon dioxide based indicator layers. In one illustrative embodiment, a stressed silicon, nitrogen and carbon-containing layer may be combined with a stressed silicon and nitrogen-containing layer, wherein the carbon species provides a prominent endpoint detection signal.
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