An embodiment of the present invention is directed to a circuit including a data relay stage configurable to receive primary data via a primary data interface, a primary clock having a frequency FP and a secondary clock having a frequency FS′. The primary data is received over a fixed periodic interval TI and at a rate substantially equal to FP. The amount of primary data received over TI is known to be N. The data relay stage is further configurable to provide secondary data via a secondary data interface based on the primary data and the secondary clock. The circuit also includes a phase-locked loop (PLL) circuit configurable to receive an interval reference signal having a frequency FI substantially equal to 1/TI. The PLL circuit is also configurable to provide the secondary clock based on the interval reference signal.