Invention Grant
US07881894B2 Method and circuit for local clock generation and smartcard including it thereon 有权
用于本地时钟产生的方法和电路以及包括其上的智能卡

Method and circuit for local clock generation and smartcard including it thereon
Abstract:
One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2i−1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2i−1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2i−1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.
Information query
Patent Agency Ranking
0/0