Invention Grant
- Patent Title: Memory structure with word line buffers
- Patent Title (中): 具有字线缓冲器的存储器结构
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Application No.: US12128122Application Date: 2008-05-28
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Publication No.: US07881126B2Publication Date: 2011-02-01
- Inventor: Pantas Sutardja
- Applicant: Pantas Sutardja
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C8/00

Abstract:
A memory comprises a plurality of memory cells. A row decoder module selectively drives word lines using a voltage level to access selected ones of the memory cells. A first regeneration module selectively pulls the voltage level on one of the word lines to one of first and second predetermined voltage levels. At least one of the memory cells of the one of the word lines is located between the first regeneration module and the row decoder module.
Public/Granted literature
- US20080298140A1 MEMORY STRUCTURE WITH WORD LINE BUFFERS Public/Granted day:2008-12-04
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