A shallow trench isolation structure for integrated circuits. The structure includes a semiconductor substrate and a buffered oxide layer overlying the semiconductor substrate. A pad nitride layer is overlying the buffered oxide layer. An implanted region is formed around a perimeter of the trench region. A trench region is formed within the semiconductor substrate. The trench region has a bottom width of less than 0.13 microns and an upper width of less than 0.13 microns. A rounded edge region is within a portion of the semiconductor substrate surrounding a periphery of the trench region. The rounded edges have a radius of curvature greater than about 0.02 um. A planarized high density plasma fill material is formed within the trench region. The structure has a P-well region within the semiconductor substrate and bordering a vicinity of the trench region. A channel region is within the P-well region within the semiconductor substrate. The implanted region has a concentration of more than double an amount of impurities as impurities in the channel region.