Invention Grant
- Patent Title: Scanned memory testing of multi-port memory arrays
- Patent Title (中): 多端口内存阵列的扫描内存测试
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Application No.: US12349652Application Date: 2009-01-07
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Publication No.: US07865786B2Publication Date: 2011-01-04
- Inventor: Robert Glen Gerowitz , Kenichi Tsuchiya
- Applicant: Robert Glen Gerowitz , Kenichi Tsuchiya
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Winstead, P.C.
- Main IPC: G11C29/32
- IPC: G11C29/32 ; G11C29/46

Abstract:
A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.
Public/Granted literature
- US20090116323A1 SCANNED MEMORY TESTING OF MULTI-PORT MEMORY ARRAYS Public/Granted day:2009-05-07
Information query
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