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US07865786B2 Scanned memory testing of multi-port memory arrays 失效
多端口内存阵列的扫描内存测试

Scanned memory testing of multi-port memory arrays
Abstract:
A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.
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