Invention Grant
- Patent Title: Information processing method and instruction generating method
- Patent Title (中): 信息处理方法和指令生成方法
-
Application No.: US11797685Application Date: 2007-05-07
-
Publication No.: US07865706B2Publication Date: 2011-01-04
- Inventor: Naoya Ichinose
- Applicant: Naoya Ichinose
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2006-133471 20060512
- Main IPC: G06F15/00
- IPC: G06F15/00

Abstract:
According to a generated instruction, the present invention provides an information processing method for performing processing by using a CPU that comprises at least one register. The method comprises the steps of: judging whether or not each of the registers is valid in the instruction; identifying a register whose value is changed by an interrupt processing generated in the instruction; and calculating a number of registers to be evacuated in the interrupt processing based on valid judgment information of the register and identification information of the register whose value is changed by the interrupt processing, and determining whether or not the interrupt processing is permitted based on a calculation result thereof.
Public/Granted literature
- US20070266230A1 Information processing method and instruction generating method Public/Granted day:2007-11-15
Information query