Invention Grant
US07865650B2 Processor with coherent bus controller at perpendicularly intersecting axial bus layout for communication among SMP compute elements and off-chip I/O elements
有权
具有相干总线控制器的处理器，用于垂直相交的轴向总线布局，用于SMP计算元件和片外I / O元件之间的通信
- Patent Title: Processor with coherent bus controller at perpendicularly intersecting axial bus layout for communication among SMP compute elements and off-chip I/O elements
- Patent Title (中): 具有相干总线控制器的处理器，用于垂直相交的轴向总线布局，用于SMP计算元件和片外I / O元件之间的通信
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Application No.: US12060670Application Date: 2008-04-01
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Publication No.: US07865650B2Publication Date: 2011-01-04
- Inventor: Charles Francis Marino , John Thomas Holloway, Jr. , Praveen S Reddy , William John Starke
- Applicant: Charles Francis Marino , John Thomas Holloway, Jr. , Praveen S Reddy , William John Starke
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Matt Talpis; Mark P Kahler
- Main IPC: G06F13/14
- IPC: G06F13/14
Abstract:
A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of the processor chip. The I/O interfaces may be distributed uniformly along portions of the perimeter.
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