A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts as a candidate interconnection for a failure, an interconnection passing an analysis region, out of a plurality of interconnections, using interconnection information to describe a configuration of interconnections in the semiconductor device by a pattern data group of interconnection patterns in respective layers, and, for extracting the candidate interconnection, it performs an equipotential trace of the interconnection patterns using the pattern data group, thereby extracting the candidate interconnection. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.