Invention Grant
- Patent Title: Multi level inhibit scheme
- Patent Title (中): 多级抑制方案
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Application No.: US12059506Application Date: 2008-03-31
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Publication No.: US07864585B2Publication Date: 2011-01-04
- Inventor: Satoru Tamada
- Applicant: Satoru Tamada
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Priority: JP2008-034423 20080215
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C7/02

Abstract:
Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the memory cells and biased to predetermined bias levels. Methods of manipulation of isolated channel region bias levels through applied word line bias voltages affecting a program inhibit effect, for example, are also disclosed.
Public/Granted literature
- US20090207657A1 MULTI LEVEL INHIBIT SCHEME Public/Granted day:2009-08-20
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