Invention Grant
- Patent Title: Multilayer wiring structure for memory circuit
- Patent Title (中): 存储电路的多层布线结构
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Application No.: US12171650Application Date: 2008-07-11
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Publication No.: US07863751B2Publication Date: 2011-01-04
- Inventor: Satoru Takase
- Applicant: Satoru Takase
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-186977 20070718
- Main IPC: H01L29/40
- IPC: H01L29/40
Abstract:
A semiconductor integrated circuit device includes: a semiconductor substrate, on which diffusion layers are formed; and multilayered wirings stacked above the semiconductor substrate to be connected to the diffusion layers via contact plugs, wherein a first wring and a second wiring formed thereabove are connected to the diffusion layers via first contact plug(s) and second contact plugs, respectively, and the number of the second contact plugs arrayed in parallel is set to be greater than that of the first contact plug(s).
Public/Granted literature
- US20090020785A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2009-01-22
Information query
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