Invention Grant
US07863721B2 Method and apparatus for wafer level integration using tapered vias 有权
使用锥形通孔进行晶片级整合的方法和装置

Method and apparatus for wafer level integration using tapered vias
Abstract:
A semiconductor device has first and second wafers having bond pads. The bond pad of the second wafer is connected to the bond pad of the first wafer using a conductive adhesive. A first interconnect structure is formed within the second wafer and includes a first via formed in a back surface of the second wafer to expose the bond pad of the second wafer. A first metal layer is formed conformally over the first via and is in electrical contact with the bond pad of the second wafer. A third wafer is mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer. A second interconnect structure is formed over a backside of the third wafer opposite the front surface. The second interconnect structure is electrically connected to the first metal layer.
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