Invention Grant
US07863721B2 Method and apparatus for wafer level integration using tapered vias
有权
使用锥形通孔进行晶片级整合的方法和装置
- Patent Title: Method and apparatus for wafer level integration using tapered vias
- Patent Title (中): 使用锥形通孔进行晶片级整合的方法和装置
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Application No.: US12137242Application Date: 2008-06-11
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Publication No.: US07863721B2Publication Date: 2011-01-04
- Inventor: Nathapong Suthiwongsunthorn , Pandi Chelvam Marimuthu
- Applicant: Nathapong Suthiwongsunthorn , Pandi Chelvam Marimuthu
- Applicant Address: SG
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG
- Agent Robert D. Atkins
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A semiconductor device has first and second wafers having bond pads. The bond pad of the second wafer is connected to the bond pad of the first wafer using a conductive adhesive. A first interconnect structure is formed within the second wafer and includes a first via formed in a back surface of the second wafer to expose the bond pad of the second wafer. A first metal layer is formed conformally over the first via and is in electrical contact with the bond pad of the second wafer. A third wafer is mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer. A second interconnect structure is formed over a backside of the third wafer opposite the front surface. The second interconnect structure is electrically connected to the first metal layer.
Public/Granted literature
- US20090309235A1 Method and Apparatus for Wafer Level Integration Using Tapered Vias Public/Granted day:2009-12-17
Information query
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