Invention Grant
- Patent Title: Dual oxide stress liner
- Patent Title (中): 双重氧化应力衬垫
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Application No.: US11956043Application Date: 2007-12-13
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Publication No.: US07863646B2Publication Date: 2011-01-04
- Inventor: Michael P. Belyansky , Xiangdong Chen , Thomas W. Dyer , Geng Wang , Haining S. Yang
- Applicant: Michael P. Belyansky , Xiangdong Chen , Thomas W. Dyer , Geng Wang , Haining S. Yang
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb I.P. Law Firm, LLC
- Agent Yuanmin Cai, Esq.
- Main IPC: H01L31/111
- IPC: H01L31/111 ; H01L21/00
Abstract:
A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.
Public/Granted literature
- US20090152638A1 DUAL OXIDE STRESS LINER Public/Granted day:2009-06-18
Information query
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