System and method for implementing a design flow for a programmable hardware element (PHE) that includes a processor. A graphical program (GP) is received, where the GP specifies performance criteria. The GP is mapped for deployment, with a first portion targeted for execution by the processor, and a second portion targeted for implementation in the PHE. A determination is made as to whether the graphical program meets the performance criteria. If not, the GP is remapped for deployment, including identifying and specifying the sub-portion for implementation in the PHE, thereby moving the sub-portion from the first portion to the second portion, and/or identifying and specifying the sub-portion for execution on the processor, thereby moving the sub-portion from the second portion to the first portion. The determining and remapping is repeated one or more times until the performance criteria are met. The first and second portions are deployed to the PHE.