A microprocessor includes a random number generator circuit (RNG) within its instruction set architecture (ISA). An RNG buffer accumulates zero or more bytes of random data generated by the RNG. An RNG counter maintains a count of the accumulated random data bytes. An instruction translator translates instructions of the ISA. The ISA includes a distinct instruction that instructs the microprocessor to write the bytes from the buffer to a first user-visible register of the microprocessor and to load the count from the counter to a second user-visible register of the microprocessor. The count is unspecified by the instruction and may be between zero or more. In another embodiment, the instruction instructs the microprocessor to store a number of random data bytes specified from the buffer to a destination specified by the instruction, wherein the specified number may be greater than the maximum amount of bytes the buffer can hold.