Invention Grant
- Patent Title: Semiconductor integrated circuit
- Patent Title (中): 半导体集成电路
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Application No.: US11872283Application Date: 2007-10-15
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Publication No.: US07848399B2Publication Date: 2010-12-07
- Inventor: Shuichi Takada
- Applicant: Shuichi Takada
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Turocy & Watson, LLP
- Priority: JP2006-286426 20061020
- Main IPC: H04B17/00
- IPC: H04B17/00 ; H04L25/00

Abstract:
A semiconductor integrated circuit has first and second delay circuits that have n (n is an integer equal to or larger than 2) delay elements connected in series, respectively, and in which an identical input signal is inputted to delay elements at a first stage and output signals of delay elements at a kth (k is an integer satisfying a condition 1≦k≦n−1) stage are inputted to delay elements at a k+1th stage and a detection circuit that has n edge detecting units and a readout unit and in which a jth (j is an integer satisfying a condition 1≦j≦n) edge detecting unit is inputted with an output signal of a delay element at a jth stage of the first delay circuit and an output signal of a delay element at an n−j+1th stage of the second delay circuit, detects whether periods of rising or falling changes of the two signals overlap, and counts a number of times of the detection, and the readout unit reads out the counted number of times of the detection.
Public/Granted literature
- US20080095224A1 SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2008-04-24
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