Invention Grant
US07848175B2 Calibration of memory driver with offset in a memory controller and memory device interface in a communication bus 失效
在通信总线中的存储器控​​制器和存储器件接口中校准具有偏移的存储器驱动器

Calibration of memory driver with offset in a memory controller and memory device interface in a communication bus
Abstract:
A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. The memory device, which is typically the device initializing a bit level voltage on a data net, is adjusted through altering what appears to be the reference voltage value to the memory device. A current driven to the memory device is varied in small increments while impedance training is rerun until a desired value is achieved to set the 0 level voltage on the data net.
Information query
Patent Agency Ranking
0/0