Invention Grant
US07847365B2 MOSFET with isolation structure for monolithic integration and fabrication method thereof
有权
具有用于单片集成的隔离结构的MOSFET及其制造方法
- Patent Title: MOSFET with isolation structure for monolithic integration and fabrication method thereof
- Patent Title (中): 具有用于单片集成的隔离结构的MOSFET及其制造方法
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Application No.: US11913037Application Date: 2005-10-14
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Publication No.: US07847365B2Publication Date: 2010-12-07
- Inventor: Chih-Feng Huang , Tuo-Hsin Chien , Jenn-Yu Lin , Ta-yung Yang
- Applicant: Chih-Feng Huang , Tuo-Hsin Chien , Jenn-Yu Lin , Ta-yung Yang
- Applicant Address: TW Taipei Hsien
- Assignee: System General Corp.
- Current Assignee: System General Corp.
- Current Assignee Address: TW Taipei Hsien
- Agency: J.C. Patents
- Priority: CN200510066874 20050428
- International Application: PCT/CN2005/001686 WO 20051014
- International Announcement: WO2006/114029 WO 20061102
- Main IPC: H01L29/78
- IPC: H01L29/78
Abstract:
A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.
Public/Granted literature
- US20090050962A1 MOSFET WITH ISOLATION STRUCTURE FOR MONOLITHIC INTEGRATION AND FABRICATION METHOD THEREOF Public/Granted day:2009-02-26
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