Invention Grant
- Patent Title: Methods and systems to write to soft error upset tolerant latches
- Patent Title (中): 写入软错误不耐受锁存器的方法和系统
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Application No.: US12240318Application Date: 2008-09-29
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Publication No.: US07808845B2Publication Date: 2010-10-05
- Inventor: Dan Krueger , Kevin Duda , Frank Verdico
- Applicant: Dan Krueger , Kevin Duda , Frank Verdico
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Garrett IP, LLC
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
Methods and systems to write to redundant storage latches, or storage cells, including soft error upset tolerant latches and feedback-interlocked redundant storage cells, including to write a logic value to one of a plurality of same sense storage nodes, and to write a complementary logic value to a selected one of a plurality of opposite sense storage nodes responsive to the logic value. Remaining storage nodes may be written to through circuitry within the storage cell. Logic values may be output substantially simultaneously with corresponding write operations. A system may include a multiple logic level write circuit to write to the first same sense storage node, and first and second single logic level write circuits to write to the first and second opposite sense storage nodes, respectively.
Public/Granted literature
- US20100080072A1 METHODS AND SYSTEMS TO WRITE TO SOFT ERROR UPSET TOLERANT LATCHES Public/Granted day:2010-04-01
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