Invention Grant
- Patent Title: Individual wafer history storage for overlay corrections
- Patent Title (中): 单独的晶圆历史存储用于覆盖修正
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Application No.: US11498268Application Date: 2006-08-03
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Publication No.: US07808613B2Publication Date: 2010-10-05
- Inventor: Joeri Lof
- Applicant: Joeri Lof
- Applicant Address: NL Veldhoven
- Assignee: ASML Netherlands B.V.
- Current Assignee: ASML Netherlands B.V.
- Current Assignee Address: NL Veldhoven
- Agency: Pillsbury Winthrop Shaw Pittman LLP
- Main IPC: G03B27/42
- IPC: G03B27/42

Abstract:
The invention relates to a device manufacturing method comprising identifying a substrate to be processed, performing a manufacturing step of a patterned layer on the substrate, and storing a substrate process history for the substrate. The history may comprise a correction map comprising position errors caused by the manufacturing step. Identifying the substrate may be done by reading an identification sign present on the substrate or by reading an identification code of a lot comprising the substrate and determining a sequence number of the substrate in the lot. Alignment of the substrate with respect to a patterning device of a lithographic apparatus may be corrected using information of the substrate process history. Alternatively or additionally, measured overlay errors may be corrected per substrate using information of the substrate process history.
Public/Granted literature
- US20080030701A1 Individual wafer history storage for overlay corrections Public/Granted day:2008-02-07
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