Invention Grant
- Patent Title: Method for manufacturing a layer arrangement and layer arrangement
- Patent Title (中): 制造层布置和层布置的方法
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Application No.: US11786770Application Date: 2007-04-12
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Publication No.: US07807563B2Publication Date: 2010-10-05
- Inventor: Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
- Applicant: Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
- Applicant Address: DE Munich
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Munich
- Agency: Slater & Matsil, L.L.P.
- Priority: DE102004050391 20041015
- Main IPC: H01L23/58
- IPC: H01L23/58

Abstract:
In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.
Public/Granted literature
- US20070246831A1 Method for manufacturing a layer arrangement and layer arrangement Public/Granted day:2007-10-25
Information query
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