Invention Grant
- Patent Title: Method and structure for self aligned formation of a gate polysilicon layer
- Patent Title (中): 栅极多晶硅层自对准形成的方法和结构
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Application No.: US11623048Application Date: 2007-01-12
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Publication No.: US07807532B2Publication Date: 2010-10-05
- Inventor: Li Jiang , Ying Shao , Libbert Peng , Auter Wu
- Applicant: Li Jiang , Ying Shao , Libbert Peng , Auter Wu
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Townsend and Townsend and Crew LLP
- Priority: CN200610025646 20060412
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method for processing semiconductor devices includes providing a semiconductor substrate. The method includes forming a pad oxide layer overlying the substrate and forming a silicon nitride layer overlying the pad oxide layer. The method includes forming a trench region extending through an entirety of a portion of the silicon nitride layer and extends into a depth of the semiconductor substrate. The method also includes filling the trench region with an oxide material. The oxide material extends from a bottom portion of the trench region to an upper surface of the silicon nitride layer. The method includes planarizing the oxide material and selectively removing the silicon nitride layer to form an isolation structure. A polysilicon material is deposited overlying the isolation structure. The polysilicon material is planarized to expose a top portion of the isolation structure and form a first electrode and a second electrode structures separated by a portion of the isolation structure.
Public/Granted literature
- US20070243685A1 METHOD AND STRUCTURE FOR SELF ALIGNED FORMATION OF A GATE POLYSILICON LAYER Public/Granted day:2007-10-18
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