A memory system and related method of operation are disclosed. The memory system includes a memory configured to generate a data strobe signal including “(n/2)+1” clock signals, where “n” is a number of base data blocks in read data synchronously transferred by the memory during a read operation, and a memory controller configured to receive the read data, receive the data strobe signal, delay the data strobe signal to generate a delayed data strobe signal, and synchronously output “n/2” sampled data blocks to a requesting device in relation to the delayed data strobe signal.