Invention Grant
- Patent Title: Mixed-mode PLL
- Patent Title (中): 混合模式PLL
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Application No.: US12349647Application Date: 2009-01-07
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Publication No.: US07791417B2Publication Date: 2010-09-07
- Inventor: Ping-Ying Wang , Jing-Hon Conan Zhan
- Applicant: Ping-Ying Wang , Jing-Hon Conan Zhan
- Applicant Address: TW Hsin-Chu
- Assignee: MediaTek Inc.
- Current Assignee: MediaTek Inc.
- Current Assignee Address: TW Hsin-Chu
- Agency: Thomas, Kayden, Horstemeyer & Risley
- Main IPC: H03L7/06
- IPC: H03L7/06
Abstract:
A mixed-mode PLL is disclosed. The mixed-mode PLL comprises an analog phase correction path and a digital frequency correction path. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit.
Public/Granted literature
- US20090174491A1 Mixed-Mode PLL Public/Granted day:2009-07-09
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