Invention Grant
- Patent Title: Semiconductor integrated circuit
- Patent Title (中): 半导体集成电路
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Application No.: US12357720Application Date: 2009-01-22
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Publication No.: US07791381B2Publication Date: 2010-09-07
- Inventor: Takashi Ohyabu
- Applicant: Takashi Ohyabu
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2008-024024 20080204
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
A semiconductor integrated circuit according to the present invention comprises a clock tree circuit for delay-adjusting a clock signal using various delay amounts, and a clock synchronizing circuit to which the delay-adjusted clock signal is supplied. The clock tree circuit comprises a first clock tree cell provided in a poststage of a clock signal introducing terminal, a second clock tree cell provided in a prestage of the clock synchronizing circuit and a poststage of the first clock tree cell, and a clock ramification point provided in a prestage of the second clock tree cell. The clock synchronizing circuit comprises a first clock synchronizing circuit to which the clock signal delay-adjusted by the second clock tree cell and thereafter outputted from the clock tree circuit is supplied, and a second clock synchronizing circuit to which the clock signal outputted from the clock tree circuit at the clock ramification point is supplied.
Public/Granted literature
- US20090195274A1 SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2009-08-06
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