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US07790545B2 Semiconductor device having a polysilicon electrode including amorphizing, recrystallising, and removing part of the polysilicon electrode 有权
具有包括多晶硅电极的非晶化，再结晶和去除部分的多晶硅电极的半导体器件

  • Patent Title: Semiconductor device having a polysilicon electrode including amorphizing, recrystallising, and removing part of the polysilicon electrode
  • Patent Title (中): 具有包括多晶硅电极的非晶化，再结晶和去除部分的多晶硅电极的半导体器件
  • Application No.: US11917103
    Application Date: 2006-06-13
  • Publication No.: US07790545B2
    Publication Date: 2010-09-07
  • Inventor: Bartlomiej J. Pawlak
  • Applicant: Bartlomiej J. Pawlak
  • Applicant Address: NL Eindhoven
  • Assignee: NXP B.V.
  • Current Assignee: NXP B.V.
  • Current Assignee Address: NL Eindhoven
  • Priority: EP05105323 20050616
  • International Application: PCT/IB2006/051879 WO 20060613
  • International Announcement: WO2006/134553 WO 20061221
  • Main IPC: H01L21/8238
  • IPC: H01L21/8238 ;  H01L21/302 ;  H01L21/461
Semiconductor device having a polysilicon electrode including amorphizing, recrystallising, and removing part of the polysilicon electrode
Abstract:
A method of manufacturing a semiconductor device such as a MOS transistor. The device comprises a polysilicon gate (10) and doped regions (22,24) formed in a semiconductor substrate (12), separated by a channel region (26). The exposed surface of the semiconductor substrate is amorphized, by ion bombardment for example, so as to inhibit subsequent diffusion of the dopant ions during thermal annealing. Low thermal budgets are favored for the activation and polysilicon regrowth to ensure an abrupt doping profile for the source/drain regions. As a consequence an upper portion (10b) of the gate electrode remains amorphous. The upper portion of the gate electrode is removed so as to allow a low resistance contact to be made with the polysilicon lower portion (10a).
Abstract(Chinese):

一种制造诸如MOS晶体管的半导体器件的方法。 该器件包括多晶硅栅极（10）和形成在半导体衬底（12）中的掺杂区域（22,24），由沟道区域（26）隔开。 半导体衬底的暴露表面是非晶化的，例如通过离子轰击，以便抑制在热退火期间掺杂剂离子随后的扩散。 低热预算有利于激活和多晶硅再生，以确保源极/漏极区域的突变掺杂分布。 结果，栅电极的上部（10b）保持无定形。 去除栅电极的上部，以便与多晶硅下部（10a）进行低电阻接触。

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Espacenet
IPC分类:
H 电学
H01 基本电气元件
H01L 半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00 专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70 .由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77 ..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78 ...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82 ....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822 .....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232 ......场效应工艺
H01L21/8234 .......MIS工艺
H01L21/8238 ........互补场效应晶体管，例如CMOS
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