Method and structure for forming multiple self-aligned gate stacks for logic devices

Invention Grant

US07790541B2 Method and structure for forming multiple self-aligned gate stacks for logic devices 有权

Title translation: 用于形成用于逻辑器件的多个自对准栅极堆叠的方法和结构

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Patent Title: Method and structure for forming multiple self-aligned gate stacks for logic devices
Patent Title (中): 用于形成用于逻辑器件的多个自对准栅极堆叠的方法和结构
Application No.: US11950095

Application Date: 2007-12-04
Publication No.: US07790541B2

Publication Date: 2010-09-07
Inventor: Bruce B. Doris , Mahender Kumar , Werner A. Rausch , Robin Van Den Nieuwenhuizen
Applicant: Bruce B. Doris , Mahender Kumar , Werner A. Rausch , Robin Van Den Nieuwenhuizen
Applicant Address: US NY Armonk US CA Sunnyvale
Assignee: International Business Machines Corporation,Advanced Micro Devices, Inc. (AMD)
Current Assignee: International Business Machines Corporation,Advanced Micro Devices, Inc. (AMD)
Current Assignee Address: US NY Armonk US CA Sunnyvale
Agency: Cantor Colburn LLP
Agent Daniel Schnurmann
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L21/336 ; H01L21/76

Method and structure for forming multiple self-aligned gate stacks for logic devices

Abstract:

A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.

Abstract(Chinese):

一种用于形成多个自对准栅极堆叠的方法，所述方法包括：在衬底的第一部分上形成第一组栅极堆叠层，在所述衬底的邻近所述第一部分的第二部分上形成第二组栅极堆叠层蚀刻以形成设置在衬底的第一部分和第二部分之间的沟槽，并用绝缘材料填充沟槽。

Public/Granted literature

US20090140347A1 METHOD AND STRUCTURE FOR FORMING MULTIPLE SELF-ALIGNED GATE STACKS FOR LOGIC DEVICES Public/Granted day:2009-06-04

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS