Invention Grant
US07769166B2 Dual mode AES implementation to support single and multiple AES operations
有权
双模AES实现，支持单AES和多AES操作
- Patent Title: Dual mode AES implementation to support single and multiple AES operations
- Patent Title (中): 双模AES实现，支持单AES和多AES操作
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Application No.: US11509361Application Date: 2006-08-24
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Publication No.: US07769166B2Publication Date: 2010-08-03
- Inventor: Nasima Parveen , Venkatesh Balasubramanian
- Applicant: Nasima Parveen , Venkatesh Balasubramanian
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agent Christopher P. Maiorana, PC
- Main IPC: H04L9/32
- IPC: H04L9/32 ; H04L9/08 ; H04K1/00 ; H04K1/04 ; G06F1/00 ; G06F7/72
Abstract:
An apparatus comprising a mode circuit and an encryption circuit. The mode circuit may be configured to selectively provide register input data on an output signal when in a first mode and memory data on the output signal when in a second mode. The encryption circuit may be configured to interchangeably encrypt/decrypt between the register input data and the memory data.
Public/Granted literature
- US20080069339A1 Dual mode AES implementation to support single and multiple AES operations Public/Granted day:2008-03-20
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