Invention Grant
US07769048B2 Link and lane level packetization scheme of encoding in serial links
有权
串行链路编码的链路和车道级分组方案
- Patent Title: Link and lane level packetization scheme of encoding in serial links
- Patent Title (中): 串行链路编码的链路和车道级分组方案
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Application No.: US12145696Application Date: 2008-06-25
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Publication No.: US07769048B2Publication Date: 2010-08-03
- Inventor: Debendra Das Sharma
- Applicant: Debendra Das Sharma
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Carrie A. Boone, P.C.
- Main IPC: H04J3/00
- IPC: H04J3/00 ; G06F11/00 ; H04N11/02

Abstract:
A novel encoding scheme is disclosed, enabling the physical layer to identify packet boundaries by looking at a few selected bits while improving the error detection capability and maintaining low overhead for low power states. By eliminating the overhead of 8b/10b encoding for the physical layer, the encoding scheme achieves better error detection ability than current 8b/10b encoding. Further, the novel encoding scheme provides additional error detection capability, a low overhead mechanism to exit low power states, and a mechanism to handle problematic packets.
Public/Granted literature
- US20090323722A1 LINK AND LANE LEVEL PACKETIZATION SCHEME OF ENCODING IN SERIAL LINKS Public/Granted day:2009-12-31
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