Invention Grant
- Patent Title: FIN-FET device structure
- Patent Title (中): FIN-FET器件结构
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Application No.: US11334974Application Date: 2006-01-18
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Publication No.: US07768069B2Publication Date: 2010-08-03
- Inventor: Chung-Long Cheng , Kong-Beng Thei
- Applicant: Chung-Long Cheng , Kong-Beng Thei
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Tung & Associates
- Main IPC: H01L27/01
- IPC: H01L27/01 ; H01L27/12 ; H01L31/0392

Abstract:
A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket planarizing layer is formed as a planarizing layer, a photoresist layer formed thereupon is formed with enhanced resolution. As a result, the gate electrode is also formed with enhanced resolution. A resulting FIN-FET structure has the patterned planarizing layer formed in an inverted “U” shape upon the gate electrode.
Public/Granted literature
- US20060115947A1 Planarizing method for forming FIN-FET device Public/Granted day:2006-06-01
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