Invention Grant
- Patent Title: Layout for high density conductive interconnects
- Patent Title (中): 高密度导电互连布局
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Application No.: US12185633Application Date: 2008-08-04
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Publication No.: US07767573B2Publication Date: 2010-08-03
- Inventor: Qiang Tang , Ramin Ghodsi
- Applicant: Qiang Tang , Ramin Ghodsi
- Applicant Address: US NY Mount Kisco
- Assignee: Round Rock Research, LLC
- Current Assignee: Round Rock Research, LLC
- Current Assignee Address: US NY Mount Kisco
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y >x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry.
Public/Granted literature
- US20080290374A1 LAYOUT FOR HIGH DENSITY CONDUCTIVE INTERCONNECTS Public/Granted day:2008-11-27
Information query
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