Invention Grant
- Patent Title: Method for verifying and correcting post-OPC pattern layout
- Patent Title (中): OPC模式布局校验和校正方法
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Application No.: US11892764Application Date: 2007-08-27
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Publication No.: US07752595B2Publication Date: 2010-07-06
- Inventor: Shimon Maeda , Koujirou Ohyoshi
- Applicant: Shimon Maeda , Koujirou Ohyoshi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2006-231142 20060828
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A pattern producing method includes specifying a first pattern and a second pattern obtained by modifying the first pattern, specifying a correction area based on the second pattern, in a part of an area including the first pattern and the second pattern, producing at least a part of the first pattern, which is included in the correction area, as a correction target pattern, producing a part of the first or second pattern, which is not included in the correction area, as a correction reference pattern, correcting the correction target pattern on the basis of the correction target pattern and the correction reference pattern, and producing a pattern based on the corrected correction target pattern and the second pattern.
Public/Granted literature
- US20090053619A1 Pattern producing method, semiconductor device manufacturing method and program Public/Granted day:2009-02-26
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