Invention Grant
- Patent Title: Semiconductor memory device having a plurality of chips and capability of outputting a busy signal
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Application No.: US11904560Application Date: 2007-09-27
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Publication No.: US07751259B2Publication Date: 2010-07-06
- Inventor: Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
- Applicant: Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2001-198132 20010629; JP2001-377408 20011211; JP2002-159518 20020531
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.
Public/Granted literature
- US20080170437A1 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal Public/Granted day:2008-07-17
Information query
