Invention Grant
US07751215B2 Semiconductor device and electric apparatus having a semiconductor layer divided into a plurality of square subregions 有权
具有被划分为多个平方子区域的半导体层的半导体装置和电气装置

  • Patent Title: Semiconductor device and electric apparatus having a semiconductor layer divided into a plurality of square subregions
  • Patent Title (中): 具有被划分为多个平方子区域的半导体层的半导体装置和电气装置
  • Application No.: US11995072
    Application Date: 2006-07-07
  • Publication No.: US07751215B2
    Publication Date: 2010-07-06
  • Inventor: Makoto Kitabatake
  • Applicant: Makoto Kitabatake
  • Applicant Address: JP Osaka
  • Assignee: Panasonic Corporation
  • Current Assignee: Panasonic Corporation
  • Current Assignee Address: JP Osaka
  • Agency: McDermott Will & Emery LLP
  • Priority: JP2005-200517 20050708
  • International Application: PCT/JP2006/313575 WO 20060707
  • International Announcement: WO2007/007670 WO 20070118
  • Main IPC: H02M7/537
  • IPC: H02M7/537 H02M7/5387
Semiconductor device and electric apparatus having a semiconductor layer divided into a plurality of square subregions
Abstract:
The present invention provides a semiconductor device and an electric apparatus each of which can realize both high-speed switching operation and energy loss reduction and excels in resistance to current concentration based on a counter electromotive voltage generated by, for example, an inductance load of the electric apparatus. A semiconductor device (100) of the present invention includes: a semiconductor layer (3) made of a first conductivity type wide band-gap semiconductor; a transistor cell (101T) in which a vertical field effect transistor (102) is formed, the vertical field effect transistor (102) causing a charge carrier to move in a thickness direction of the semiconductor layer (3); and a diode cell (101S) in which a Schottky diode (103) is formed, the Schottky diode (103) being formed such that a Schottky electrode (9) forms a Schottky junction with the semiconductor layer (3), wherein the semiconductor layer 3 is divided into a plurality of square subregions (101T and 101S) based on virtual border lines (30) in plan view, and includes the subregion (101T) as the transistor cell and the subregion (101S) as the diode cell.
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