A pulse generation circuit for outputting to an output terminal (OT) includes an inverter delay circuit (IDC) for processing a start signal with a predetermined delay; a first switching circuit (SC) adapted to connect the OT to a first voltage when a logical product of the IDC is true, and to connect the OT to a second voltage when a logical sum of the IDC is false; a second SC adapted to connect the OT to the first voltage when a logical product of the IDC is true, and to connect the OT to the second voltage when a logical sum of the IDC is false; and a start signal control circuit adapted to input the start signal to the IDC with a delay when the first SC is activated, and to input the start signal to the IDC without the delay when the second SC is activated.