Invention Grant
- Patent Title: Negative voltage detection circuit and semiconductor integrated circuit
- Patent Title (中): 负电压检测电路和半导体集成电路
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Application No.: US12235175Application Date: 2008-09-22
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Publication No.: US07733730B2Publication Date: 2010-06-08
- Inventor: Yoshiaki Hashiba
- Applicant: Yoshiaki Hashiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-245063 20070921
- Main IPC: G11C7/04
- IPC: G11C7/04

Abstract:
A negative voltage detection circuit including first and second MOS transistor circuits configured to change a dimension size of a transistor based on a control signal, a first comparator circuit, a gate electrode of the second MOS transistor circuit commonly coupled to the gate electrode of the first MOS transistor circuit forming a current mirror circuit, a resistive divider supplied with a negative voltage to be detected, and coupled to the end of the current path of the second MOS transistor circuit to generate a second voltage, a second voltage comparator circuit to compare the second voltage with a reference voltage and to generate a detection signal corresponding to the value of the negative voltage, and a detection circuit for detecting a temperature or power supply voltage, generate the control signal corresponding to the detection result, and supply the control signal to the first and second MOS transistor circuits.
Public/Granted literature
- US20090080281A1 NEGATIVE VOLTAGE DETECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2009-03-26
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