Methods, systems and devices for testing flash memory dies are disclosed. According to some embodiments, during the post-wafer sort stage of device manufacture, a plurality of flash memory devices, each of which includes a flash controller die and at least one flash memory die associated with a common housing, are subjected to a testing process, for examples, a batch testing process or a mass testing process. During testing, a respective flash controller residing on a respective flash controller die executes at least one test program to test one or more respective flash memory dies of the respective flash device. A testing system including at least 100 of the flash memory devices and a mass-testing board is disclosed. Furthermore, flash memory devices where the flash controller is operative to test one or more of the flash memory dies are disclosed. Exemplary testing includes but is not limited to bad block testing.