Invention Grant
- Patent Title: Future execution prefetching technique and architecture
- Patent Title (中): 未来执行预取技术和架构
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Application No.: US11335829Application Date: 2006-01-20
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Publication No.: US07730263B2Publication Date: 2010-06-01
- Inventor: Martin Burtscher , Ilya Ganusov
- Applicant: Martin Burtscher , Ilya Ganusov
- Applicant Address: US NY Ithaca
- Assignee: Cornell Research Foundation, Inc.
- Current Assignee: Cornell Research Foundation, Inc.
- Current Assignee Address: US NY Ithaca
- Agency: Jones, Tullar & Cooper P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F13/28

Abstract:
A prefetching technique referred to as future execution (FE) dynamically creates a prefetching thread for each active thread in a processor by simply sending a copy of all committed, register-writing instructions in a primary thread to an otherwise idle processor. On the way to the second processor, a value predictor replaces each predictable instruction with a load immediate instruction, where the immediate is the predicted result that the instruction is likely to produce during its nth next dynamic execution. Executing this modified instruction stream (i.e., the prefetching thread) in another processor allows computation of the future results of the instructions that are not directly predictable. This causes the issuance of prefetches into the shared memory hierarchy, thereby reducing the primary thread's memory access time and speeding up the primary thread's execution.
Public/Granted literature
- US20070174555A1 Future execution prefetching technique and architecture Public/Granted day:2007-07-26
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