Invention Grant
- Patent Title: Block decoding methods and apparatus
- Patent Title (中): 块解码方法和装置
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Application No.: US11084502Application Date: 2005-03-18
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Publication No.: US07712013B2Publication Date: 2010-05-04
- Inventor: Meir Griniasty , Moti Altahan
- Applicant: Meir Griniasty , Moti Altahan
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H03M13/03
- IPC: H03M13/03

Abstract:
In an embodiment, a method includes performing a redundancy check to determine if a baseline bit sequence is compliant. When the baseline bit sequence is not compliant, the method additionally includes performing an iterative process until a compliant, candidate bit sequence is identified. The iterative process includes identifying one or more existing branches within a conceptual tree diagram, calculating scores for potential paths branching from the one or more existing branches, and performing a subsequent redundancy check on a next candidate bit sequence, which corresponds to a potential path that has a next lowest score, to determine if the next candidate bit sequence is compliant.
Public/Granted literature
- US20060212784A1 Block decoding methods and apparatus Public/Granted day:2006-09-21
Information query
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