Invention Grant
- Patent Title: Semiconductor structure for low parasitic gate capacitance
- Patent Title (中): 用于低寄生栅极电容的半导体结构
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Application No.: US11738666Application Date: 2007-04-23
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Publication No.: US07709910B2Publication Date: 2010-05-04
- Inventor: William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
- Applicant: William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent H. Daniel Schnurmann
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.
Public/Granted literature
- US20080258234A1 SEMICONDUCTOR STRUCTURE FOR LOW PARASITIC GATE CAPACITANCE Public/Granted day:2008-10-23
Information query
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