Invention Grant
- Patent Title: ESD structure
- Patent Title (中): ESD结构
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Application No.: US11267175Application Date: 2005-11-07
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Publication No.: US07709907B2Publication Date: 2010-05-04
- Inventor: Stephen Joseph Gaul , Michael D. Church , James Edwin Vinson
- Applicant: Stephen Joseph Gaul , Michael D. Church , James Edwin Vinson
- Applicant Address: US CA Milpitas
- Assignee: Intersil Americas Inc.
- Current Assignee: Intersil Americas Inc.
- Current Assignee Address: US CA Milpitas
- Main IPC: H01L27/088
- IPC: H01L27/088

Abstract:
An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the formation of metal silicides into the dislocation region. The spacing of the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation region is produced by providing additional lateral opposed second gate regions or oxide barrier layer extending from the oxide layer into the adjacent regions of the substrate region and the first gate region extending therebetween. Both the first gate region and the two second gate regions or barrier layer are used in the self-aligned processing of the source and drain regions. The first gate region defines the length of the channel, while the two opposed second gate regions or barrier layer define the width of the channel region. The second gate portion or barrier extends sufficiently into the substrate region to space the width of the channel from the adjacent edge of the opening in the oxide.
Public/Granted literature
- US20060097293A1 ESD structure Public/Granted day:2006-05-11
Information query
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