Invention Grant
US07709396B2 Integral patterning of large features along with array using spacer mask patterning process flow
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使用间隔物掩模图案化工艺流程的大型特征与阵列的整体图案化
- Patent Title: Integral patterning of large features along with array using spacer mask patterning process flow
- Patent Title (中): 使用间隔物掩模图案化工艺流程的大型特征与阵列的整体图案化
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Application No.: US12234101Application Date: 2008-09-19
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Publication No.: US07709396B2Publication Date: 2010-05-04
- Inventor: Christopher Dennis Bencher , Jing Tang
- Applicant: Christopher Dennis Bencher , Jing Tang
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Townsend and Townsend and Crew, LLP
- Main IPC: H01L21/214
- IPC: H01L21/214 ; H01L21/483
Abstract:
Embodiments of the present invention pertain to methods of forming patterned features on a substrate having an increased density (i.e. reduced pitch) as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask while also allowing both the width of the patterned features and spacing (trench width) between the patterned features to vary within an integrated circuit.
Public/Granted literature
- US20100075503A1 INTEGRAL PATTERNING OF LARGE FEATURES ALONG WITH ARRAY USING SPACER MASK PATTERNING PROCESS FLOW Public/Granted day:2010-03-25
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